1. Field of the Invention
Example embodiments of the present invention relate to a hub and methods thereof, and more particularly to a hub for testing memory and methods thereof.
2. Description of the Related Art
A plurality of memory devices in a memory module may be mounted on a printed circuit board (PCB) in a Single In-line Memory Module (SIMM) or a Dual In-line Memory Module (DIMM). A SIMM may include memory chips mounted on a single side of the PCB, while the DIMM may include memory chips mounted on both sides of the PCB. A DIMM may be classified as either a Fully Buffered DIMM (FBDIMM) or a Registered DIMM.
In microprocessor systems, the FBDIMM may be used to convert received higher-speed packets into memory commands. The FMDIMM may also be used to synchronize incoming/outgoing signals.
A FBDIMM memory system may include a plurality of slots and a plurality of FBDIMMs mounted on the slots. The plurality of FBDIMMs may be tested separately (e.g., before being mounted) in order to determine whether the mounted FBDIMMs will operate normally.
FBDIMM channel architecture may use a point-to-point connection or protocol and FBDIMM memory systems may not depend on an input/output (I/O) speed of a Dynamic Random Access Memory (DRAM), which may allow a higher number of modules to be mounted on the FBDIMM memory system. Unlike Registered DIMMs, FBDIMMs may include a hub in place of a Phase Locked Loop (PLL) and register combination.
The FBDIMM hub may receive packets and may de-packetize the received packets (e.g., extract information from the received packets) to provide addresses, memory commands and/or data to a plurality of memory devices mounted on the FBDIMM. The hub may packetize data (e.g., collect data and generate data packets with the collected data) received from the memory device and may output the packetized data to a host.
The FBDIMM hub may include a memory Built-In Self Test (BIST) circuit for testing the memory device. The BIST circuit may include a logic circuit for generating a test pattern. In the FBDIMM, the memory device may be tested using a BIST circuit or, alternatively, a transparent mode test.
A special mode selection signal may be received at a conventional BIST circuit from outside the memory module (e.g., the FBDIMM) which may trigger test logic, stored in the hub, to test the memory device. The test logic may test the memory device by generating a pseudo random test pattern using a fixed test pattern (e.g., stored in the hub), a Linear Feedback Shift Register (LFSR), etc.
In the transparent mode test, an address, a memory command and test data may be received from a test apparatus (e.g., an external device) and may be written directly to the memory device in response to a control signal. The hub may relay the received signals (e.g., address, memory command, test data, etc.) to the memory device. Thus, the hub need not de-packetize the received signals (e.g., address, memory command, test data, etc.) in the transparent mode test. In the transparent mode test, the hub may read test data from the memory device to be tested and may compare the read test data with the generated test data. If the comparison indicates a match, a PASS signal may be generated. Otherwise, if the comparison does not indicate a match, a FAIL signal may be generated.
In the conventional transparent mode test, the test data pattern may not be generated from the hub of the memory module, but rather may be received from an external test apparatus (e.g., not part of the FBDIMM). Because of hardware complexity, it may be difficult to include the LFSR for generating the pseudo random pattern in the external testing apparatus. Thus, in the conventional transparent mode test, the memory device may be tested with a fixed data pattern, and not a random data pattern. Testing memory devices with non-random data may be less effective as compared to random data testing.